/*******************************************************************************
 *
 * Copyright (c) 2004-2008 by Vivante Corp.  All rights reserved.
 *
 * The material in this file is confidential and contains trade secrets of
 * Vivante Corporation.  This is proprietary information owned by Vivante
 * Corporation.  No part of this work may be disclosed, reproduced, copied,
 * transmitted, or used in any way for any purpose, without the express
 * written permission of Vivante Corporation.
 *
 ******************************************************************************/

/*******************************************************************************
 *
 * This file is automatically generated on Mon Apr 13 01:22:32 2009
 *
 * Any changes made to this file are lost at the next compile run!
 * So better make sure you update the source .r files instead!
 *
 ******************************************************************************/

////////////////////////////////////////////////////////////////////////////////
//                            ~~~~~~~~~~~~~~~~~~~~                            //
//                            Module HostInterface                            //
//                            ~~~~~~~~~~~~~~~~~~~~                            //
////////////////////////////////////////////////////////////////////////////////

// Register AQHiClockControl.
// ~~~~~~~~~~~~~~~~~~~~~~~~~

// Clock control register.

#define AQHiClockControlRegAddrs                                          0x0000
#define AQ_HI_CLOCK_CONTROL_Address                                      0x00000
#define AQ_HI_CLOCK_CONTROL_MSB                                               15
#define AQ_HI_CLOCK_CONTROL_LSB                                                0
#define AQ_HI_CLOCK_CONTROL_Count                                              1
#define AQ_HI_CLOCK_CONTROL_FieldMask                                 0x000307FF
#define AQ_HI_CLOCK_CONTROL_ReadMask                                  0x000307FF
#define AQ_HI_CLOCK_CONTROL_WriteMask                                 0x000007FF
#define AQ_HI_CLOCK_CONTROL_ResetValue                                0x00000100

// Disable 3D clock.
#define AQ_HI_CLOCK_CONTROL_CLK3D_DIS                                        0:0
#define AQ_HI_CLOCK_CONTROL_CLK3D_DIS_End                                      0
#define AQ_HI_CLOCK_CONTROL_CLK3D_DIS_Start                                    0

// Disable 2D clock.
#define AQ_HI_CLOCK_CONTROL_CLK2D_DIS                                        1:1
#define AQ_HI_CLOCK_CONTROL_CLK2D_DIS_End                                      1
#define AQ_HI_CLOCK_CONTROL_CLK2D_DIS_Start                                    1

#define AQ_HI_CLOCK_CONTROL_FSCALE_VAL                                       8:2
#define AQ_HI_CLOCK_CONTROL_FSCALE_VAL_End                                     8
#define AQ_HI_CLOCK_CONTROL_FSCALE_VAL_Start                                   2

#define AQ_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD                                  9:9
#define AQ_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_End                                9
#define AQ_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_Start                              9

// Disables clock gating for rams.
#define AQ_HI_CLOCK_CONTROL_DISABLE_RAM_CLOCK_GATING                       10:10
#define AQ_HI_CLOCK_CONTROL_DISABLE_RAM_CLOCK_GATING_End                      10
#define AQ_HI_CLOCK_CONTROL_DISABLE_RAM_CLOCK_GATING_Start                    10

// 3D pipe is idle.
#define AQ_HI_CLOCK_CONTROL_IDLE3_D                                        16:16
#define AQ_HI_CLOCK_CONTROL_IDLE3_D_End                                       16
#define AQ_HI_CLOCK_CONTROL_IDLE3_D_Start                                     16

// 2D pipe is idle.
#define AQ_HI_CLOCK_CONTROL_IDLE2_D                                        17:17
#define AQ_HI_CLOCK_CONTROL_IDLE2_D_End                                       17
#define AQ_HI_CLOCK_CONTROL_IDLE2_D_Start                                     17

// Register AQHiIdle.
// ~~~~~~~~~~~~~~~~~

// Idle status register.

#define AQHiIdleRegAddrs                                                  0x0001
#define AQ_HI_IDLE_Address                                               0x00004
#define AQ_HI_IDLE_MSB                                                        15
#define AQ_HI_IDLE_LSB                                                         0
#define AQ_HI_IDLE_Count                                                       1
#define AQ_HI_IDLE_FieldMask                                          0x800000FF
#define AQ_HI_IDLE_ReadMask                                           0x800000FF
#define AQ_HI_IDLE_WriteMask                                          0x00000000
#define AQ_HI_IDLE_ResetValue                                         0x00000000

// FE is idle.
#define AQ_HI_IDLE_IDLE_FE                                                   0:0
#define AQ_HI_IDLE_IDLE_FE_End                                                 0
#define AQ_HI_IDLE_IDLE_FE_Start                                               0

// DE is idle.
#define AQ_HI_IDLE_IDLE_DE                                                   1:1
#define AQ_HI_IDLE_IDLE_DE_End                                                 1
#define AQ_HI_IDLE_IDLE_DE_Start                                               1

// PE is idle.
#define AQ_HI_IDLE_IDLE_PE                                                   2:2
#define AQ_HI_IDLE_IDLE_PE_End                                                 2
#define AQ_HI_IDLE_IDLE_PE_Start                                               2

// SH is idle.
#define AQ_HI_IDLE_IDLE_SH                                                   3:3
#define AQ_HI_IDLE_IDLE_SH_End                                                 3
#define AQ_HI_IDLE_IDLE_SH_Start                                               3

// PA is idle.
#define AQ_HI_IDLE_IDLE_PA                                                   4:4
#define AQ_HI_IDLE_IDLE_PA_End                                                 4
#define AQ_HI_IDLE_IDLE_PA_Start                                               4

// SE is idle.
#define AQ_HI_IDLE_IDLE_SE                                                   5:5
#define AQ_HI_IDLE_IDLE_SE_End                                                 5
#define AQ_HI_IDLE_IDLE_SE_Start                                               5

// RA is idle.
#define AQ_HI_IDLE_IDLE_RA                                                   6:6
#define AQ_HI_IDLE_IDLE_RA_End                                                 6
#define AQ_HI_IDLE_IDLE_RA_Start                                               6

// TX is idle.
#define AQ_HI_IDLE_IDLE_TX                                                   7:7
#define AQ_HI_IDLE_IDLE_TX_End                                                 7
#define AQ_HI_IDLE_IDLE_TX_Start                                               7

// AXI is in low power mode.
#define AQ_HI_IDLE_AXI_LP                                                  31:31
#define AQ_HI_IDLE_AXI_LP_End                                                 31
#define AQ_HI_IDLE_AXI_LP_Start                                               31

// Register AQAxiConfig.
// ~~~~~~~~~~~~~~~~~~~~
#define AQAxiConfigRegAddrs                                               0x0002
#define AQ_AXI_CONFIG_Address                                            0x00008
#define AQ_AXI_CONFIG_MSB                                                     15
#define AQ_AXI_CONFIG_LSB                                                      0
#define AQ_AXI_CONFIG_Count                                                    1
#define AQ_AXI_CONFIG_FieldMask                                       0x0000FFFF
#define AQ_AXI_CONFIG_ReadMask                                        0x0000FFFF
#define AQ_AXI_CONFIG_WriteMask                                       0x0000FFFF
#define AQ_AXI_CONFIG_ResetValue                                      0x00000000

#define AQ_AXI_CONFIG_AWID                                                   3:0
#define AQ_AXI_CONFIG_AWID_End                                                 3
#define AQ_AXI_CONFIG_AWID_Start                                               0

#define AQ_AXI_CONFIG_ARID                                                   7:4
#define AQ_AXI_CONFIG_ARID_End                                                 7
#define AQ_AXI_CONFIG_ARID_Start                                               4

#define AQ_AXI_CONFIG_AWCACHE                                               11:8
#define AQ_AXI_CONFIG_AWCACHE_End                                             11
#define AQ_AXI_CONFIG_AWCACHE_Start                                            8

#define AQ_AXI_CONFIG_ARCACHE                                              15:12
#define AQ_AXI_CONFIG_ARCACHE_End                                             15
#define AQ_AXI_CONFIG_ARCACHE_Start                                           12

// Register AQAxiStatus.
// ~~~~~~~~~~~~~~~~~~~~
#define AQAxiStatusRegAddrs                                               0x0003
#define AQ_AXI_STATUS_Address                                            0x0000C
#define AQ_AXI_STATUS_MSB                                                     15
#define AQ_AXI_STATUS_LSB                                                      0
#define AQ_AXI_STATUS_Count                                                    1
#define AQ_AXI_STATUS_FieldMask                                       0x000003FF
#define AQ_AXI_STATUS_ReadMask                                        0x000003FF
#define AQ_AXI_STATUS_WriteMask                                       0x00000000
#define AQ_AXI_STATUS_ResetValue                                      0x00000000

#define AQ_AXI_STATUS_DET_RD_ERR                                             9:9
#define AQ_AXI_STATUS_DET_RD_ERR_End                                           9
#define AQ_AXI_STATUS_DET_RD_ERR_Start                                         9

#define AQ_AXI_STATUS_DET_WR_ERR                                             8:8
#define AQ_AXI_STATUS_DET_WR_ERR_End                                           8
#define AQ_AXI_STATUS_DET_WR_ERR_Start                                         8

#define AQ_AXI_STATUS_RD_ERR_ID                                              7:4
#define AQ_AXI_STATUS_RD_ERR_ID_End                                            7
#define AQ_AXI_STATUS_RD_ERR_ID_Start                                          4

#define AQ_AXI_STATUS_WR_ERR_ID                                              3:0
#define AQ_AXI_STATUS_WR_ERR_ID_End                                            3
#define AQ_AXI_STATUS_WR_ERR_ID_Start                                          0

// Register AQIntrAcknowledge.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~

// Interrupt acknowledge register.  Each bit represents a
// corresponding event being triggered.  Reading frmo this
// register clears the outstanding interrupt.

#define AQIntrAcknowledgeRegAddrs                                         0x0004
#define AQ_INTR_ACKNOWLEDGE_Address                                      0x00010
#define AQ_INTR_ACKNOWLEDGE_MSB                                               15
#define AQ_INTR_ACKNOWLEDGE_LSB                                                0
#define AQ_INTR_ACKNOWLEDGE_Count                                              1
#define AQ_INTR_ACKNOWLEDGE_FieldMask                                 0xFFFFFFFF
#define AQ_INTR_ACKNOWLEDGE_ReadMask                                  0xFFFFFFFF
#define AQ_INTR_ACKNOWLEDGE_WriteMask                                 0x00000000
#define AQ_INTR_ACKNOWLEDGE_ResetValue                                0x00000000

#define AQ_INTR_ACKNOWLEDGE_INTR_VEC                                        31:0
#define AQ_INTR_ACKNOWLEDGE_INTR_VEC_End                                      31
#define AQ_INTR_ACKNOWLEDGE_INTR_VEC_Start                                     0

// Register AQIntrEnbl.
// ~~~~~~~~~~~~~~~~~~~

// Interrupt enable register.  Each bit enables a corresponding
// event.

#define AQIntrEnblRegAddrs                                                0x0005
#define AQ_INTR_ENBL_Address                                             0x00014
#define AQ_INTR_ENBL_MSB                                                      15
#define AQ_INTR_ENBL_LSB                                                       0
#define AQ_INTR_ENBL_Count                                                     1
#define AQ_INTR_ENBL_FieldMask                                        0xFFFFFFFF
#define AQ_INTR_ENBL_ReadMask                                         0xFFFFFFFF
#define AQ_INTR_ENBL_WriteMask                                        0xFFFFFFFF
#define AQ_INTR_ENBL_ResetValue                                       0x00000000

#define AQ_INTR_ENBL_INTR_ENBL_VEC                                          31:0
#define AQ_INTR_ENBL_INTR_ENBL_VEC_End                                        31
#define AQ_INTR_ENBL_INTR_ENBL_VEC_Start                                       0

// Register AQIdent.
// ~~~~~~~~~~~~~~~~

// Identification register.

#define AQIdentRegAddrs                                                   0x0006
#define AQ_IDENT_Address                                                 0x00018
#define AQ_IDENT_MSB                                                          15
#define AQ_IDENT_LSB                                                           0
#define AQ_IDENT_Count                                                         1
#define AQ_IDENT_FieldMask                                            0xFFFFFFFF
#define AQ_IDENT_ReadMask                                             0xFFFFFFFF
#define AQ_IDENT_WriteMask                                            0x00000000
#define AQ_IDENT_ResetValue                                           0x00000000

// Family value.
#define AQ_IDENT_FAMILY                                                    31:24
#define AQ_IDENT_FAMILY_End                                                   31
#define AQ_IDENT_FAMILY_Start                                                 24
#define   AQ_IDENT_FAMILY_GC500                                             0x01
#define   AQ_IDENT_FAMILY_GC520                                             0x02
#define   AQ_IDENT_FAMILY_GC530                                             0x03
#define   AQ_IDENT_FAMILY_GC400                                             0x04
#define   AQ_IDENT_FAMILY_GC450                                             0x05
#define   AQ_IDENT_FAMILY_GC600                                             0x08
#define   AQ_IDENT_FAMILY_GC700                                             0x09
#define   AQ_IDENT_FAMILY_GC800                                             0x0C
#define   AQ_IDENT_FAMILY_GC1000                                            0x10

// Product value.
#define AQ_IDENT_PRODUCT                                                   23:16
#define AQ_IDENT_PRODUCT_End                                                  23
#define AQ_IDENT_PRODUCT_Start                                                16

// Revision value.
#define AQ_IDENT_REVISION                                                  15:12
#define AQ_IDENT_REVISION_End                                                 15
#define AQ_IDENT_REVISION_Start                                               12

// Technology value.
#define AQ_IDENT_TECHNOLOGY                                                 11:8
#define AQ_IDENT_TECHNOLOGY_End                                               11
#define AQ_IDENT_TECHNOLOGY_Start                                              8

// Customer value.
#define AQ_IDENT_CUSTOMER                                                    7:0
#define AQ_IDENT_CUSTOMER_End                                                  7
#define AQ_IDENT_CUSTOMER_Start                                                0

// Register GCFeatures.
// ~~~~~~~~~~~~~~~~~~~

// Shows which features are enabled in this chip.

#define GCFeaturesRegAddrs                                                0x0007
#define GC_FEATURES_Address                                              0x0001C
#define GC_FEATURES_MSB                                                       15
#define GC_FEATURES_LSB                                                        0
#define GC_FEATURES_Count                                                      1
#define GC_FEATURES_FieldMask                                         0x001FFFFF
#define GC_FEATURES_ReadMask                                          0x001FFFFF
#define GC_FEATURES_WriteMask                                         0x00000000
#define GC_FEATURES_ResetValue                                        0x00000000

// Fast clear.
#define GC_FEATURES_FAST_CLEAR                                               0:0
#define GC_FEATURES_FAST_CLEAR_End                                             0
#define GC_FEATURES_FAST_CLEAR_Start                                           0
#define   GC_FEATURES_FAST_CLEAR_NONE                                        0x0
#define   GC_FEATURES_FAST_CLEAR_AVAILABLE                                   0x1

// Full-screen anti-aliasing.
#define GC_FEATURES_SPECIAL_ANTI_ALIASING                                    1:1
#define GC_FEATURES_SPECIAL_ANTI_ALIASING_End                                  1
#define GC_FEATURES_SPECIAL_ANTI_ALIASING_Start                                1
#define   GC_FEATURES_SPECIAL_ANTI_ALIASING_NONE                             0x0
#define   GC_FEATURES_SPECIAL_ANTI_ALIASING_AVAILABLE                        0x1

// 3D pipe.
#define GC_FEATURES_PIPE_3D                                                  2:2
#define GC_FEATURES_PIPE_3D_End                                                2
#define GC_FEATURES_PIPE_3D_Start                                              2
#define   GC_FEATURES_PIPE_3D_NONE                                           0x0
#define   GC_FEATURES_PIPE_3D_AVAILABLE                                      0x1

// DXT texture compression.
#define GC_FEATURES_DXT_TEXTURE_COMPRESSION                                  3:3
#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_End                                3
#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_Start                              3
#define   GC_FEATURES_DXT_TEXTURE_COMPRESSION_NONE                           0x0
#define   GC_FEATURES_DXT_TEXTURE_COMPRESSION_AVAILABLE                      0x1

// Debug registers.
#define GC_FEATURES_DEBUG_MODE                                               4:4
#define GC_FEATURES_DEBUG_MODE_End                                             4
#define GC_FEATURES_DEBUG_MODE_Start                                           4
#define   GC_FEATURES_DEBUG_MODE_NONE                                        0x0
#define   GC_FEATURES_DEBUG_MODE_AVAILABLE                                   0x1

// Depth compression.
#define GC_FEATURES_ZCOMPRESSION                                             5:5
#define GC_FEATURES_ZCOMPRESSION_End                                           5
#define GC_FEATURES_ZCOMPRESSION_Start                                         5
#define   GC_FEATURES_ZCOMPRESSION_NONE                                      0x0
#define   GC_FEATURES_ZCOMPRESSION_AVAILABLE                                 0x1

// YUV 4:2:0 support in filter blit.
#define GC_FEATURES_YUV420_FILTER                                            6:6
#define GC_FEATURES_YUV420_FILTER_End                                          6
#define GC_FEATURES_YUV420_FILTER_Start                                        6
#define   GC_FEATURES_YUV420_FILTER_NONE                                     0x0
#define   GC_FEATURES_YUV420_FILTER_AVAILABLE                                0x1

// MSAA support.
#define GC_FEATURES_MSAA                                                     7:7
#define GC_FEATURES_MSAA_End                                                   7
#define GC_FEATURES_MSAA_Start                                                 7
#define   GC_FEATURES_MSAA_NONE                                              0x0
#define   GC_FEATURES_MSAA_AVAILABLE                                         0x1

// Shows if there is a display controller in the IP.
#define GC_FEATURES_DC                                                       8:8
#define GC_FEATURES_DC_End                                                     8
#define GC_FEATURES_DC_Start                                                   8
#define   GC_FEATURES_DC_NONE                                                0x0
#define   GC_FEATURES_DC_AVAILABLE                                           0x1

// Shows if there is 2D engine.
#define GC_FEATURES_PIPE_2D                                                  9:9
#define GC_FEATURES_PIPE_2D_End                                                9
#define GC_FEATURES_PIPE_2D_Start                                              9
#define   GC_FEATURES_PIPE_2D_NONE                                           0x0
#define   GC_FEATURES_PIPE_2D_AVAILABLE                                      0x1

// ETC1 texture compression.
#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION                               10:10
#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_End                              10
#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_Start                            10
#define   GC_FEATURES_ETC1_TEXTURE_COMPRESSION_NONE                          0x0
#define   GC_FEATURES_ETC1_TEXTURE_COMPRESSION_AVAILABLE                     0x1

// Shows if the IP has HD scaler.
#define GC_FEATURES_FAST_SCALER                                            11:11
#define GC_FEATURES_FAST_SCALER_End                                           11
#define GC_FEATURES_FAST_SCALER_Start                                         11
#define   GC_FEATURES_FAST_SCALER_NONE                                       0x0
#define   GC_FEATURES_FAST_SCALER_AVAILABLE                                  0x1

// Shows if the IP has HDR support.
#define GC_FEATURES_HIGH_DYNAMIC_RANGE                                     12:12
#define GC_FEATURES_HIGH_DYNAMIC_RANGE_End                                    12
#define GC_FEATURES_HIGH_DYNAMIC_RANGE_Start                                  12
#define   GC_FEATURES_HIGH_DYNAMIC_RANGE_NONE                                0x0
#define   GC_FEATURES_HIGH_DYNAMIC_RANGE_AVAILABLE                           0x1

// YUV 4:2:0 tiler is available.
#define GC_FEATURES_YUV420_TILER                                           13:13
#define GC_FEATURES_YUV420_TILER_End                                          13
#define GC_FEATURES_YUV420_TILER_Start                                        13
#define   GC_FEATURES_YUV420_TILER_NONE                                      0x0
#define   GC_FEATURES_YUV420_TILER_AVAILABLE                                 0x1

// Second level clock gating is available.
#define GC_FEATURES_MODULE_CG                                              14:14
#define GC_FEATURES_MODULE_CG_End                                             14
#define GC_FEATURES_MODULE_CG_Start                                           14
#define   GC_FEATURES_MODULE_CG_NONE                                         0x0
#define   GC_FEATURES_MODULE_CG_AVAILABLE                                    0x1

// IP is configured to have minimum area.
#define GC_FEATURES_MIN_AREA                                               15:15
#define GC_FEATURES_MIN_AREA_End                                              15
#define GC_FEATURES_MIN_AREA_Start                                            15
#define   GC_FEATURES_MIN_AREA_NONE                                          0x0
#define   GC_FEATURES_MIN_AREA_AVAILABLE                                     0x1

// IP does not have early-Z.
#define GC_FEATURES_NO_EZ                                                  16:16
#define GC_FEATURES_NO_EZ_End                                                 16
#define GC_FEATURES_NO_EZ_Start                                               16
#define   GC_FEATURES_NO_EZ_NONE                                             0x0
#define   GC_FEATURES_NO_EZ_AVAILABLE                                        0x1

// IP does not have 422 texture input format.
#define GC_FEATURES_NO422_TEXTURE                                          17:17
#define GC_FEATURES_NO422_TEXTURE_End                                         17
#define GC_FEATURES_NO422_TEXTURE_Start                                       17
#define   GC_FEATURES_NO422_TEXTURE_NONE                                     0x0
#define   GC_FEATURES_NO422_TEXTURE_AVAILABLE                                0x1

// IP supports interleaving depth and color buffers.
#define GC_FEATURES_BUFFER_INTERLEAVING                                    18:18
#define GC_FEATURES_BUFFER_INTERLEAVING_End                                   18
#define GC_FEATURES_BUFFER_INTERLEAVING_Start                                 18
#define   GC_FEATURES_BUFFER_INTERLEAVING_NONE                               0x0
#define   GC_FEATURES_BUFFER_INTERLEAVING_AVAILABLE                          0x1

// Supports byte write in 2D.
#define GC_FEATURES_BYTE_WRITE_2D                                          19:19
#define GC_FEATURES_BYTE_WRITE_2D_End                                         19
#define GC_FEATURES_BYTE_WRITE_2D_Start                                       19
#define   GC_FEATURES_BYTE_WRITE_2D_NONE                                     0x0
#define   GC_FEATURES_BYTE_WRITE_2D_AVAILABLE                                0x1

// IP does not have 2D scaler.
#define GC_FEATURES_NO_SCALER                                              20:20
#define GC_FEATURES_NO_SCALER_End                                             20
#define GC_FEATURES_NO_SCALER_Start                                           20
#define   GC_FEATURES_NO_SCALER_NONE                                         0x0
#define   GC_FEATURES_NO_SCALER_AVAILABLE                                    0x1

// Register GCChipId.
// ~~~~~~~~~~~~~~~~~

// Shows the ID for the chip in BCD.

#define GCChipIdRegAddrs                                                  0x0008
#define GC_CHIP_ID_Address                                               0x00020
#define GC_CHIP_ID_MSB                                                        15
#define GC_CHIP_ID_LSB                                                         0
#define GC_CHIP_ID_Count                                                       1
#define GC_CHIP_ID_FieldMask                                          0xFFFFFFFF
#define GC_CHIP_ID_ReadMask                                           0xFFFFFFFF
#define GC_CHIP_ID_WriteMask                                          0x00000000
#define GC_CHIP_ID_ResetValue                                         0x00000000

// Id.
#define GC_CHIP_ID_ID                                                       31:0
#define GC_CHIP_ID_ID_End                                                     31
#define GC_CHIP_ID_ID_Start                                                    0

// Register GCChipRev.
// ~~~~~~~~~~~~~~~~~~

// Shows the revision for the chip in BCD.

#define GCChipRevRegAddrs                                                 0x0009
#define GC_CHIP_REV_Address                                              0x00024
#define GC_CHIP_REV_MSB                                                       15
#define GC_CHIP_REV_LSB                                                        0
#define GC_CHIP_REV_Count                                                      1
#define GC_CHIP_REV_FieldMask                                         0xFFFFFFFF
#define GC_CHIP_REV_ReadMask                                          0xFFFFFFFF
#define GC_CHIP_REV_WriteMask                                         0x00000000
#define GC_CHIP_REV_ResetValue                                        0x00000000

// Revision.
#define GC_CHIP_REV_REV                                                     31:0
#define GC_CHIP_REV_REV_End                                                   31
#define GC_CHIP_REV_REV_Start                                                  0

// Register GCChipDate.
// ~~~~~~~~~~~~~~~~~~~

// Shows the release date for the IP.

#define GCChipDateRegAddrs                                                0x000A
#define GC_CHIP_DATE_Address                                             0x00028
#define GC_CHIP_DATE_MSB                                                      15
#define GC_CHIP_DATE_LSB                                                       0
#define GC_CHIP_DATE_Count                                                     1
#define GC_CHIP_DATE_FieldMask                                        0xFFFFFFFF
#define GC_CHIP_DATE_ReadMask                                         0xFFFFFFFF
#define GC_CHIP_DATE_WriteMask                                        0x00000000
#define GC_CHIP_DATE_ResetValue                                       0x00000000

// Date.
#define GC_CHIP_DATE_DATE                                                   31:0
#define GC_CHIP_DATE_DATE_End                                                 31
#define GC_CHIP_DATE_DATE_Start                                                0

// Register GCChipTime.
// ~~~~~~~~~~~~~~~~~~~

// Shows the release time for the IP.

#define GCChipTimeRegAddrs                                                0x000B
#define GC_CHIP_TIME_Address                                             0x0002C
#define GC_CHIP_TIME_MSB                                                      15
#define GC_CHIP_TIME_LSB                                                       0
#define GC_CHIP_TIME_Count                                                     1
#define GC_CHIP_TIME_FieldMask                                        0xFFFFFFFF
#define GC_CHIP_TIME_ReadMask                                         0xFFFFFFFF
#define GC_CHIP_TIME_WriteMask                                        0x00000000
#define GC_CHIP_TIME_ResetValue                                       0x00000000

// Time.
#define GC_CHIP_TIME_TIME                                                   31:0
#define GC_CHIP_TIME_TIME_End                                                 31
#define GC_CHIP_TIME_TIME_Start                                                0

// Register GCChipCustomer.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Shows the customer and group for the IP.

#define GCChipCustomerRegAddrs                                            0x000C
#define GC_CHIP_CUSTOMER_Address                                         0x00030
#define GC_CHIP_CUSTOMER_MSB                                                  15
#define GC_CHIP_CUSTOMER_LSB                                                   0
#define GC_CHIP_CUSTOMER_Count                                                 1
#define GC_CHIP_CUSTOMER_FieldMask                                    0xFFFFFFFF
#define GC_CHIP_CUSTOMER_ReadMask                                     0xFFFFFFFF
#define GC_CHIP_CUSTOMER_WriteMask                                    0x00000000
#define GC_CHIP_CUSTOMER_ResetValue                                   0x00000000

// Company.
#define GC_CHIP_CUSTOMER_COMPANY                                           31:16
#define GC_CHIP_CUSTOMER_COMPANY_End                                          31
#define GC_CHIP_CUSTOMER_COMPANY_Start                                        16

// Group.
#define GC_CHIP_CUSTOMER_GROUP                                              15:0
#define GC_CHIP_CUSTOMER_GROUP_End                                            15
#define GC_CHIP_CUSTOMER_GROUP_Start                                           0

// Register GCMinorFeatures0.
// ~~~~~~~~~~~~~~~~~~~~~~~~~

// Shows which minor features are enabled in this chip.

#define GCMinorFeatures0RegAddrs                                          0x000D
#define GC_MINOR_FEATURES0_Address                                       0x00034
#define GC_MINOR_FEATURES0_MSB                                                15
#define GC_MINOR_FEATURES0_LSB                                                 0
#define GC_MINOR_FEATURES0_Count                                               1
#define GC_MINOR_FEATURES0_FieldMask                                  0x0000003F
#define GC_MINOR_FEATURES0_ReadMask                                   0x0000003F
#define GC_MINOR_FEATURES0_WriteMask                                  0x00000000
#define GC_MINOR_FEATURES0_ResetValue                                 0x00000000

// Special LOD calculation when MSAA is on.
#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD                                  5:5
#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_End                                5
#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_Start                              5
#define   GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_NONE                           0x0
#define   GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_AVAILABLE                      0x1

// Driver hack is not needed.
#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER                         4:4
#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_End                       4
#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_Start                     4
#define   GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_NONE                  0x0
#define   GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_AVAILABLE             0x1

// Supports 8Kx8K textures.
#define GC_MINOR_FEATURES0_TEXTURE8_K                                        3:3
#define GC_MINOR_FEATURES0_TEXTURE8_K_End                                      3
#define GC_MINOR_FEATURES0_TEXTURE8_K_Start                                    3
#define   GC_MINOR_FEATURES0_TEXTURE8_K_NONE                                 0x0
#define   GC_MINOR_FEATURES0_TEXTURE8_K_AVAILABLE                            0x1

// Configurable endianness support.
#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG                                 2:2
#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_End                               2
#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_Start                             2
#define   GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_NONE                          0x0
#define   GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_AVAILABLE                     0x1

// Dual Return Bus from HI to clients.
#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS                                   1:1
#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_End                                 1
#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_Start                               1
#define   GC_MINOR_FEATURES0_DUAL_RETURN_BUS_NONE                            0x0
#define   GC_MINOR_FEATURES0_DUAL_RETURN_BUS_AVAILABLE                       0x1

// Y flipping capability is added to resolve.
#define GC_MINOR_FEATURES0_FLIP_Y                                            0:0
#define GC_MINOR_FEATURES0_FLIP_Y_End                                          0
#define GC_MINOR_FEATURES0_FLIP_Y_Start                                        0
#define   GC_MINOR_FEATURES0_FLIP_Y_NONE                                     0x0
#define   GC_MINOR_FEATURES0_FLIP_Y_AVAILABLE                                0x1

// Register GCCacheControl.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Not used.

#define GCCacheControlRegAddrs                                            0x000E
#define GC_CACHE_CONTROL_Address                                         0x00038
#define GC_CACHE_CONTROL_MSB                                                  15
#define GC_CACHE_CONTROL_LSB                                                   0
#define GC_CACHE_CONTROL_Count                                                 1
#define GC_CACHE_CONTROL_FieldMask                                    0xFFFFFFFF
#define GC_CACHE_CONTROL_ReadMask                                     0xFFFFFFFF
#define GC_CACHE_CONTROL_WriteMask                                    0xFFFFFFFF
#define GC_CACHE_CONTROL_ResetValue                                   0x00000000

#define GC_CACHE_CONTROL_NOT_USED                                           31:0
#define GC_CACHE_CONTROL_NOT_USED_End                                         31
#define GC_CACHE_CONTROL_NOT_USED_Start                                        0

